1. Field
Various embodiments of the present invention relate to a semiconductor design technology and, more particularly, to a semiconductor memory device and an operating method thereof.
2. Description of the Related Art
Semiconductor memory devices, such as double data rate synchronous DRAM (DDR SDRAM), generally include tens of millions of memory cells for storing data. The memory cells may be arranged in an array according to a defined set of parameters. For example, semiconductor memory devices may have memory banks in which a plurality of memory cell blocks share an input/output line and perform a single read/write operation at a time.
FIG. 1 is a block diagram for explaining the inner workings of a conventional semiconductor memory device. FIG. 1 illustrates the structure of one memory bank of a semiconductor memory device. However, the semiconductor memory device may include a plurality of memory banks.
Referring to FIG. 1, the semiconductor memory device includes a memory cell array 110, a word line activation unit 120, and a column decoding unit 130. The memory cell array 110 includes a memory bank BA having a plurality of memory cells coupled to a plurality of word lines (row lines) and bit lines (column lines).
The word line activation unit 120 generates row selection signals WLs in response to a row address ADD_ROW inputted from an exterior (i.e. form an external source). The memory bank BA may activate one word line selected by the row selection signals WLs.
The column decoding unit 130 generates column selection signals YIs in response to a column address ADD_COL inputted from an exterior. The semiconductor memory may perform a read/write operation by accessing a memory cell corresponding to the column selection signals YIs among memory cells coupled to a word line activated by the row selection signals WL.
When the row address ADD_ROW is inputted from an exterior, the word line activation unit 120 selectively activates the row selection signals WLs in response to the row address ADD_ROW, so that one word line corresponding to the row address ADD_ROW is activated among the word lines of the memory bank BA. Then, when the column address ADD_COL is inputted from an exterior, the column decoding unit 130 selectively activates the column selection signals YIs in response to the column address ADD_COL, so that a bit line corresponding to the activated column selection signal is selected and data of a memory cell selected from memory cells coupled to the activated word line is sensed.
That is, for performing a read/write operation, the semiconductor memory device selects a word line and a bit line of the memory bank BA, and accesses a memory cell corresponding to the selected lines. The memory bank BA has a plurality of memory cell blocks sharing an input/output line, and activates only one word line at a time, and performs a read/write operation corresponding to the activated word line. That is, for stable operation, when data of memory cells coupled to the activated word line is transmitted to respective bit lines, a potential difference between a bit line pair is detected and amplified, and then the column selection signals YIs, based on a read/write command, is activated.
Accordingly, the semiconductor memory device having the memory bank BA structure activates one word line at a time and performs the read/write operation after a time interval corresponding to tRCD (RAS to CAS Delay, i.e., a delay time from the input of an active command to the input of a read/write command). However, such an operation may reduce the data availability of the semiconductor memory device, resulting in a decrease in operation efficiency.